1. Field of the Invention
The present invention relates generally to ring oscillators.
2. Description of the Related Art
Voltage controlled ring oscillators are a common component in digital communication systems. An exemplary application, shown in the block diagram of FIG. 1, is directed to recovery of a clock signal from a serial data input stream. The clock recovery circuit 20 includes a control loop 22 which locks a voltage controlled ring oscillator (VCO) 24 to the frequency and phase of the digital data stream 26.
The output signal 28 of the VCO 24 is compared with the data stream 26 in both a frequency comparator 30 and a phase comparator 32. The resultant difference signals 34, 36 are sent to a charge pump 40 which produces a control signal 42 that is applied to the VCO 24. The correction signal 42 is responsive to frequency and phase variations between the VCO output 28 and the data stream 26. Gain around the loop 22 causes these variations to be acceptably low. The recovered clock signal may be taken from output 28 of VCO 24 and applied to a retiming element 44, e.g., a D type flip-flop, to generate retimed data 48.
Ring oscillators typically include a ring of serially connected gates; a structure that readily lends itself to integrated circuit fabrication. The exemplary oscillator structure 50 of FIG. 2 has a number N of serially connected inverter gates 52 each having a delay T.sub.d. The output of the last inverter gate forms the input for the first inverter gate, i.e., they are connected in a ring. This structure is limited to an odd number of gates because if the number N of gates is even, the output of the last gate is in phase with the input of the first gate. This signal, fed back as an input, causes the first gate, and all subsequent gates, to latch in their current state.
If the number of inverter gates N is odd, the feedback signal causes the first inverter gate to toggle and this toggling proceeds continuously around the loop to once again toggle the first inverter gate and so on. Thus, the output of a given inverter gate will be high for N gate delays and low for a subsequent N gate delays. A signal taken from any node of the ring will have a period of 2NT.sub.d and a frequency of 1/(2NT.sub.d).
FIG. 3 is a block diagram of another ring oscillator structure 60 having serially connected gates 62 of delay T.sub.d but each having differential inputs and outputs. As opposed to the structure of FIG. 2, the structure 60 is not limited to an odd number of gates because the differential nature of the gates 62 allows inversion of signals between selected gates as indicated by the broken lines 64.
A fixed frequency ring oscillator formed of serially connected gates, e.g., as shown in FIGS. 2 and 3, can be converted to a frequency controlled oscillator by including variable elements in one or more of the gates so as to change their gate time delay in a controlled manner. Voltage variable capacitors and resistors, e.g., a field effect transistor, can be included in gates to control their output rise and fall times and, hence, their switching delay time. Effective locations for such elements include disposition in gate collectors and/or drains to vary their RC time constant and in gate bias circuitry.
Another structure for converting serially connected gates to a controlled frequency oscillator is shown in the ring oscillator 70 of FIG. 4. The block diagram of the oscillator 70 has a pair of voltage controlled delay modules 72, 74. The delay modules each include an interpolator 78 having a time delay D1 and an output Vout which is a linear combination of a pair of inputs V1, V2. One of the inputs is preceded by a serially connected delay element 80 having a time delay D2 while the other input 81 has no delay element, i.e., a zero time delay. The delay modules 72, 74 are connected in a ring, i.e., the output of module 74 is fed back to be the input of module 72, with the oscillator output 82 taken from the output of the delay module 74. Each of the delay modules 72, 74 is supplied with an early/late control 84.
In operation of each delay module 72, 74, the contribution of its two input signals V1, V2 to the output state Vout is selectively controlled by the early/late control 84. That is, the output Vout is selectively responsive to V1 only, to V2 only, or any combination therebetween. Since the input signals V1, V2 are themselves respectively responsive to a delay time of D2 and zero, the delay of each of the modules 72, 74 can be varied between D1 and D1+D2 in response to the early/late control 84. Consequently, the period of the oscillator 70 can be varied from 2D1 to 2(D1+D2) and the frequency from 1/2D1 to 1/2(D1+D2). In circuit realizations of the voltage controlled oscillator 70, the delay modules 72, 74 preferably have differential inputs and outputs to provide first order rejection of power supply variations and noise.
It is apparent that the frequency of ring oscillators, as exemplified by FIGS. 2, 3 and 4, is primarily determined by the delay through their gates. Any variation in the gate delay appears as oscillator frequency variation (jitter): an unintended frequency modulation. A major contributor to variable gate delay has been identified as power supply instability.
U.S. Pat. No. 4,617,523 addresses the effect of changing differential input voltages on output signal perturbations of differential amplifiers which are common gate elements. This patent teaches the addition of a second differential amplifier in parallel with but differentially opposed to the subject differential amplifier. This teaching actually increases gate delay susceptibility to power supply instability because twice the amplifier structure is now coupled to the instability source.
References pertaining to clock extraction as shown in FIG. 1 include Benny Lai, et al., "A Monolithic 622 Mb/s Clock Extraction Data Retiming Circuit", 1991 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 144-145 and Aaron Buchwald, et al., "A 6 GHz Integrated Phase-Locked Loop Using AlGaAs/GaAs Hererojunction Bipolar Transistors", 1992 IEEE International Solid-State Circuits Conference, pp. 98-99 and 253. References pertaining to the serial gate oscillators shown in FIGS. 2, 3 include A. W. Buchwald, et al., "High-speed Voltage-Controlled Oscillator with Quadrature Outputs", Electronic Letters, Feb. 14, 1991, Vol. 27, No. 4, pp. 309-310. References pertaining to selectable delay oscillators shown in FIG. 4 include E. H. Armstrong, "A Method of Reducing Disturbances in Radio Signaling by a System of Frequency Modulation", Proceedings IRE, Vol. 24, No. 5, May 1936, pp. 689-740 and U.S. Pat. No. 4,884,041.